The present invention is directed generally to digital apparatus, and more particularly, to apparatus that incorporates in the scan chain of a scannable circuit the state information conveyed to a nonscannable unit.
Today's state of the art in digital design often will require the incorporation of features that will allow the design to be tested--both during production and when in the field in the hands of the end user. One of the more popular test techniques used in digital designs for test implementation is what is termed a "scan based design." This involves adding logic to the design of conventional digital circuitry so that, in response to test signals, the elemental storage units (e.g., latches, register stages, flip flops, and the like) of the digital circuitry can be configured into one or more extended shift registers ("scan chains"). Test patterns ("vectors") may then be introduced ("scanned") into the scan chains so formed, and the digital circuitry returned to its standard configuration and allowed to run normally for one or more of its operating cycles. The scan chains are then reformed so that the resultant registered state of the digital system can be removed and examined.
Alternatively, the digital circuit under test can be allowed to run normally until it reaches a point in time when the scan test halts normal operation of the circuit. The scan chain configurations are then formed, and the registered state of the circuitry is removed, observed, reinstated, and the unit allowed to proceed after being returned to its standard configuration.
Scan designs provide an effective and efficient method of establishing controllability and observability over the "registered state" of the digital circuitry (i.e., the states assumed by the elemental memory units at any moment in time) in that operation of the unit or circuit under test can be stopped at any point in time, the unit reconfigured to its scan configuration, and that state retrieved, observed, and replaced. The circuit under test may then be returned to the normal operating mode and continue until it is again stopped and its registered state observed as described.
Often, designs of digital units in the current art will combine such scannable components with standard, off-the-shelf components (e.g., microprocessors, random access memories (RAMs), and the like) that are not designed to be scannable. Thus, the registered state of these standard components are, therefore, outside the controllable and observable domains of a scan test procedure. This combination of scannable components with nonscannnable components can significantly limit the testability of the overall combination.
Since such nonscannable parts cannot be included in any scan string, any initial registered state values they may hold after a scan test (Or an initialization) of a scannable part must be considered indeterminate. This indeterminate state will tend to propagate indeterminism elsewhere, forcing use of one of several remedies: (1) add extra logic to block the formation and propagation of such indeterminate state (and accept large untestable areas of circuitry); (2) add complicated test sequences following the scan to functionally eliminate the indeterminate state; or, (3) some combination of the foregoing.
It can be seen, therefore, that a need exists for the registered state of non-scannable circuitry to co-exist with scannable circuitry for testing purposes.